Many modern radio frequency (RF) receivers use a direct conversion or zero-IF (ZIF) architecture. Here an RF signal received at an antenna is fed through mixer driven by a local oscillator (LO) and subsequently filtered to produce a baseband channel demodulated output signal. One of the primary issues addressed in such ZIF receivers is the problem of DC offset. DC offset in a receiver has a number of sources, including:                Inherent random mismatch in the receiver circuitry;        Self-mixing caused by LO energy leaking back through the mixer stage to feed back to the antenna input and then re-entering the mixer stage; and        Blocker-induced, due to 2nd order non-linearity in the mixer stage causing two unwanted signals with closely spaced frequencies to produce a difference term falling within the channel filter bandwidth.        
These DC offsets, if left unmitigated, can grow to consume a significant part, or perhaps all, of the dynamic range of the receiver. Offset correction schemes for ZIF receivers can use either purely analog or hybrid analog/digital feedback or feed forward schemes to remove DC offset. Many such offset cancellation schemes have been published, for example, as disclosed in:
Feedforward Technique for Offset Cancellation in Broadband Differential Amplifiers Duy-Dong Pham, James Brinkhoff, Kai Kang, Chyuen-Wei Ang, and Fujiang Lin; and
A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband Horng-Yuan Shih, Member, IEEE, Chien-Nan Kuo, Member, IEEE, Wei-Hsien Chen, Tzu-Yi Yang, and Kai-Chenug Juang.
U.S. Pat. No. 8,380,149 discloses a DC offset canceller including a first digital-to-analog (DA) converter, a first adder, an amplifier, a comparator, an averaging circuit, and a successive approximation register. The first DA converter is configured to DA-convert first correction data into a first correction voltage. The first adder is configured to add an input signal and the first correction voltage to output a first added signal. The amplifier is configured to amplify the first added signal to output an amplified signal. The comparator is configured to compare the amplified signal and a reference voltage to output a comparison result. The averaging circuit is configured to receive the comparison results of the comparator to obtain a majority decision result by performing majority decision on logical values of the comparison results in a predetermined time period. The successive approximation register is configured to sequentially set each bit of the first correction data based on the majority decision result so that a DC offset in the amplified signal decreases.
U.S. Pat. No. 8,478,221 discloses a wireless communication receiver including a multitude of look-up tables each storing a multitude of DC offset values associated with the gains of an amplification stage disposed in the wireless communication receiver. The entries for each look-up table are estimated during a stage of the calibration phase. During such a calibration stage, for each selected gain of an amplification stage, a search logic estimates a current DC offset number and compares it to a previous DC offset estimate that is fed back to the search logic. If the difference between the current and previous estimates is less than a predefined threshold value, the current estimate is treated as being associated with the DC offset of the selected gain of the amplification stage and is stored in the look-up table. This process is repeated for each selected gain of each amplification stage of interest until the look-up tables are populated.
Also, devices such as ADF7242™ Low Power IEEE 802.15.4/Proprietary GFSK/FSK Zero-IF 2.4 GHz Transceiver IC; and ADF7241™ Low Power IEEE 802.15.4 Zero-IF 2.4 GHz Transceiver IC from Analog Devices, Inc. (Norwood, Mass.) are equipped with an offset correction loop (OCL), which cancels both static and dynamic time-varying offset voltages present in the zero-IF receiver path.
For certain modulations, such as On-Off Keying (00K), ZIF is not a suitable architecture and in these cases, low-IF (LIF) architectures are favored.
In LIF architectures, the demodulated signal is centered at a non-zero frequency. LIF receivers using an analog complex filter have inherent attenuation of DC with the level of attenuation being dependent on the center frequency, bandwidth and roll-off of the filter.
However, depending on the implementation of the LIF architecture, there can still be a requirement to limit DC offset in order to preserve dynamic range.
For example, in a receiver with very narrow band channelization, the channel filter is typically implemented in the digital domain so as to reject very large close-in interferers. This involves the use of an ADC with a dynamic range sufficient to linearly process both wanted and interfering signals. If not addressed, DC offset (both static and dynamic (time-varying)) can potentially consume a significant fraction of the ADC dynamic range.
The DC offset correction schemes referred to above are unsuitable for a low-IF receiver which implements the channel filter in the digital domain. In this case, a down converted interferer may fall anywhere within the passband of the analog anti-alias filter (AAF), including at a lower frequency than the target channel (and even including DC). Hence, any feedback or feed forward scheme which relies on low pass filtering of the signal to extract DC information to close an error correcting loop may also now have within its passband an interfering signal many orders of magnitude greater than the target channel signal. This places unacceptably large requirements for dynamic range on the correction circuitry itself.
Examples of DC offset schemes for LIF receivers include:
A CMOS DC Offset Cancellation (DOC) Circuit for PGA of Low IF Wireless Receivers Fan Xiangning, Member IEEE, Sun Yutao, Feng Yangyang discloses a DC negative feedback technique based DC offset canceller (DOC) which can be used in a CMOS programmable gain amplifier (PGA) of a low intermediate frequency (IF) receiver. However, this approach is only suitable for an analog complex filter.
U.S. Pat. No. 7,215,266 discloses cancelling static and dynamic DC offsets by combining a digital DC offset correction scheme with an analog DC offset correction scheme. A feedback-based digital DC offset correction scheme provides different adjustment levels for a plurality of discrete gain states and the analog DC offset correction scheme operates in different cancellation modes dependent on a frame structure. A digital DC offset correction scheme collects DC offset control information and provides adjustment levels. In addition, a negative-feedback based switchable high pass filter has a plurality modes of operation, where one mode of operation includes an all-pass filter.
U.S. Pat. No. 7,221,918 discloses an RF receiver comprising a radio-frequency down-converter for receiving and down-converting an input RF signal to a lower frequency analog signal (e.g., an IF signal or baseband signal) and analog processing circuitry for receiving the lower frequency analog signal from the RF down-converter and outputting a processed analog signal. The processed analog signal includes a DC-offset signal introduced by the RF down-converter and the analog processing circuitry. The RF receiver also comprises an ADC circuit for converting the processed analog signal to a sequence of digital samples and a DC-offset correction circuit for detecting the DC-offset signal in a digital output signal of the RF receiver. The DC-offset correction circuit adds a DC-offset correction signal to the lower frequency analog signal. Adding the DC-offset correction signal to the lower frequency analog signal reduces the DC-offset signal in the processed analog signal at the analog processing circuitry output.